Description:
T+SNeed LinkedinHybridThe STA requirements will be the same as the previous one (I assume you still have access to it), with the following specifics: Subsystemlevel and fullchip timing closure experience is required.General familiarity with 2nm/3nm signoff criteria is desired.The contractor will also be expected to run synthesis as part of their responsibilities.A SYN expert would be ideal, but not strictly required.
Feb 12, 2026;
from:
dice.com