Description:
Role Summary A mid to senior-level Verification Engineer responsible for developing and executing verification plans for complex ASIC and SoC designs. This role involves designing and implementing verification environments, debugging simulations, and ensuring functional coverage. The position requires a proactive approach to problem-solving and collaboration within cross-functional teams to validate hardware components effectively. Responsibilities Develop and implement UVM testbenches and veri
Jan 26, 2026;
from:
dice.com