Description:
Hi, Full Time / Permanent Role Role: Design Verification Engineer Location : Sunnyvale CA / Austin TX Candidates with AXI and PCIE or Ethernet or DDR experience. Scripting is a plus Strong understanding of SV and UVM and good debugging skills. Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
Jan 19, 2026;
from:
dice.com