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Design Verification Engineer Engineer with EDA ,RTL Architecture , CAD ,VCS and IES exp - Austin TX - Onsite work

Optimus Labs USA
Austin Full-day Temporary

Description:

Design Verification Engineer Engineer with EDA ,RTL Architecture , CAD ,VCS and IES exp - Austin TX - Onsite work Role: Front-End Infrastructure Engineer - 530091 Location: Austin, TX Duration: 6 Months + extension Client: Samsung SARC The FE Infrastructure team is seeking a highly skilled and motivated Engineer with extensive experience in Front-End (FE) flows, tools, and methodologies. This role requires deep technical expertise and experience across multiple verification tools and platforms,
Jan 16, 2026;   from: dice.com
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