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Java lead with handson coding
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Java lead with handson coding jobs in United States
(1 jobs)
Lead fpga verification engineer with uvm /verilog system-active requirement
Last week
Company
Data Capital Inc
(
+1
)
Schedule
Full-day
(
+1
)
Employment
Full-time
(
+1
)
Source
dice.com
(
+1
)
Location
California
(
+1
)
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Lead
FPGA Verification Engineer with UVM /Verilog System-Active Requirement
Data Capital Inc
Santa Clara
... : FPGA Verification Exp Strong SystemVerilog
coding
(Universal Verification Methodology)-UVM 5+ years ...
5 days ago
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