... SerDes Validation Engineer Location: San Jose, CA Duration: 12+ months contract TOP SKILLS: SerDes validation ... seeking a skilled and experienced SerDes Validation Engineer to join our team. ... in validating high-speed SerDes interfaces across various products, ...
13 days ago
... : We are looking for Firmware Validation Engineer for our client in Santa ... Clara, CA Job Title: Firmware Validation Engineer Job Location: Santa Clara, CA ... : Pay Range: $55hr - $60hrThe Firmware Validation Engineer will be responsible for designing ...
4 days ago
Description: Hi, Role: Firmware Validation Engineer (System Level) Location: Santa Clara, ... Months+ Must Have Skills Firmware Validation Engineer Skill 1 10 + Years of exp ... in C++ (70% validation and 30% development) Skill 2 6 + Years ...
4 days ago
Description: Signal Integrity Engineer- Power Integrity experience is a plus. ... HFSS, ADS, PowerSI. Experience with SERDES interfaces such as PCIe, PAM4 ... high-speed interfaces (e.g., 224G-PAM4 SerDes). Perform channel simulations (TX-to ...
12 days ago
Description: Title: PHY System Modeling Engineer - Onsite Mandatory skills: Firmware programming, ... , Python programming, DDR training algorithms, SerDes, architectural model, exceptional firmware, calibration ...
5 days ago
Description: Job Title: Hardware Testing Engineer (Board Validation Specialized) (Contract) Number of Openings ...
27 days ago
Description: Job Title: DFT Engineer (6+ Years) Location: Santa Clara, California, ... a highly skilled and motivated DFT Engineer with 6+ years of experience to ... (DFT) methodologies, test insertion, and validation for complex SoCs. You will ...
10 days ago
Description: Title: RTL Design Engineer - Onsite Mandatory skills: FPGA, design, ... , product development cycle, implementation, prototyping, validation, productization, support, architecture, design, documentation ...
20 days ago
... (AGW) is seeking a Hardware Testing Engineer - Group D for an onsite position ... . Summary: This role involves system validation and specialized hardware testing for ...
27 days ago
Description: Senior Virtual Hardware Modeling Engineer (SystemC / C++) Location: San Jose, ... a Senior Virtual Hardware Modeling Engineer to develop high-fidelity SystemC ... early system software and firmware validation, architecture exploration, and performance ...
30 days ago
... to QA or broad software validation. You will collaborate closely with ...
22 days ago
... Low Speed IO/Power Seq validation task, able to use standard ...
26 days ago
... Express and CXL IP protocols Validation and Debugging experience Lab and ...
30 days ago
Description: Manufacturing Test Engineer (Python / Linux) Location: Santa Clara, ... a Manufacturing Test Engineer (Python / Linux) (SDET) to support production validation of networking ...
11 days ago