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Java lead with handson coding jobs from the company Data capital inc in Santa Clara (3 jobs)

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Data capital inc
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Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years ...
7 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years ...
10 days ago

Lead FPGA Verification Engineer with UVM /Verilog System-Active Requirement

  • Data Capital Inc
  • Santa Clara
... : FPGA Verification Exp Strong SystemVerilog coding (Universal Verification Methodology)-UVM 5+ years ...
14 days ago

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