... EngineerIntroduction:An experienced Signal Integrity Engineer with at least 5 years of ... interface development and validation. The engineer will be working on cutting ...
8 days ago
Description: JD Digital DV within a mixed signal chip (ADC), Digital based simulation environment, Test bench not required, it is available already, Test cases to be developed. No need to develop models, Develop test plan etc.. System Verilog, Unix/Linux, ...
2 days ago
Description: Preferred Qualifications: Experience in analog/custom layout design in advanced CMOS process(2+ years FinFet experience must)Expertise in Cadence VLE/VXL,PVS, Assura and Calibre DRC/ LVS is a must.Should have hands on experience of Critical ...
25 days ago